CD4027 - Dual JK Flip Flop ZIF Socket 40 Pin If the CPD clock is

If the CPD clock is pulsed while CPU is held HIGH

PIC16F505 PIC16F506 PIC16F54 PIC16F57*PIC16F59* PIC16F627 PIC16LF627A PIC16F627APIC16F628 PIC16LF628A PIC16F628A PIC16F630PIC16F631 PIC16F631-1 PIC16F636 PIC16F636-1PIC16F639* PIC16F639-1* PIC16F648A PIC16F676PIC16F677 PIC16F677-1 PIC16F684 PIC16F685*PIC16F685-1* PIC16F687* PIC16F687*-1 PIC16F688PIC16F689* PIC16F689-1* PIC16F690* PIC16F690-1*PIC16F716 PIC16F72 PIC16F73 PIC16F74PIC16F76 PIC16F77 PIC16F737 PIC16F747PIC16F767 PIC16F777 PIC16F83 PIC16F84PIC16F84A PIC16F87 PIC16F88 PIC16F818PIC16F819 PIC16F870 PIC16F871 PIC16F872PIC16F873 PIC16F873A PIC16LF873A PIC16F874PIC16F874A PIC16F876 PIC16F876A PIC16F877PIC16F877A

Low Level Input Voltage: 0

Size limit is 2GB

TIP126 PNP Power Darlington Transistor  (80V

CD4027 - Dual JK Flip Flop ZIF Socket 40 Pin If the CPD clock isIntroduction : CD4027 Dual JK Flip Flop monolithic complementary MOS (CMOS) integrated circuits constructed with N and P channel enhancement mode transistors. Each flip flop has independent J, K, set, reset, and clock inputs and buffered Q and Q outputs. These flip flops are edge sensitive to the clock input and change state on the positive going transition of the clock pulses. Set or reset is independent of the clock and is accomplished by a high